This application is related in subject matter to U.S. application Ser. No. 08/208,586, entitled xe2x80x9cPrefabricated Semiconductor Chip Carrierxe2x80x9d, filed Mar. 11, 1994, and expressly incorporated by reference herein, and to U.S. application Ser. No. 08/487,103, entitled xe2x80x9cSemiconductor Die Carrier Having Double-Sided Die Attach Platexe2x80x9d, filed Jun. 7, 1995, and expressly incorporated by reference herein. Furthermore, this application is related to several other patent applications which are commonly owned by the Assignee of this application. Those related applications are: U.S. Design Patent Application, Ser. No. 29/081,929 entitled Computer Cabinet, U.S. patent application, Ser. No. 08/970,503 entitled Cooling System for Semiconductor Die Carrier, U.S. patent application, Ser. No. 08/970,502 entitled Interface Optimized Computer System Architecture, and U.S. patent application, Ser. No. 08/970,434 entitled Decorative Panel for Computer Enclosure, all of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a multi-chip module and, more particularly, to a multi-chip module that includes one or more interconnect dies for interconnecting integrated circuit (IC) dies in the multi-chip module and for interconnecting the IC dies to the leads of the multi-chip module.
2. Description of the Prior Art
Operation speed continues to be one of the main selling points for electronic systems, such as computers and other data processing equipment. Increases in operation speed lead to expanded capabilities in graphics, communications, and database applications, to name just a few. One way of increasing the operation speed of an electronic system is to increase the speed of the IC dies used in the electronic system. To date, a great deal of effort has been focused on developing improved designs and architectures for increasing the operation speed of the IC dies.
Several factors besides IC die design affect operation speed in modem electronic systems. For a given architecture, the temperature at which an IC die is operated affects its operation speed. In general, a cool IC die may be reliably operated at higher speeds than a hot IC die. Modern high speed dies have demanding cooling requirements, and future designs are likely to be even more demanding. Accordingly, the ability to cool IC dies is an important factor in obtaining reliable, high speed operations of electronic systems.
In addition, as the operation speeds of IC dies increase, the propagation delay of signals passing between IC dies in the electronic system becomes significant. Propagation delay increases as the length of the wiring path between IC dies increases. However, simply locating IC dies closer together to reduce the wiring path between the IC dies presents several difficulties. For one thing, configurations with a high concentration of IC dies are difficult to cool. Therefore, any reduction in propagation delay may be more than offset by a reduction in the operating speed of the IC dies.
Multi-chip modules, which are sometimes referred to as multi-chip carriers, have been proposed as a way to miniaturize electronic systems. Multi-chip modules are semiconductor die carriers that house multiple semiconductor IC dies. The multi-chip modules generally include an insulative housing that protects and supports the IC dies and a plurality of leads that extend from the housing to couple electrical signals to and from the IC dies. The IC dies are active components, such as a microprocessor die and a static random access memory (SRAM) die.
In conventional multi-chip modules, the insulative housing holds the IC dies in one of two different arrangements. In a first arrangement, the IC dies are mounted back-to-back to an insulative substrate. Alternatively, the IC dies are mounted side-by-side on a planar substrate.
The back-to-back arrangement has several deficiencies. For example, the back-to-back arrangement limits the number of IC dies that may be housed in a single package. In addition, the back-to-back arrangement does not permit efficient interconnection between the IC dies within the housing or the efficient tansfer of heat away from the IC dies. Moreover, in the back-to-back arrangement, the back of the dies are mounted to the interior of the module. This effectively traps heat in the module and, thus, limits the operation speed of the IC dies.
In the side-by-side arrangement, the IC dies in the multi-chip module are interconnected by a multilayer ceramic or multilayer printed circuit board (CB) interconnectors. However, the ceramic and PCB interconnectors are relatively expensive to manufacture. In addition, these interconnectors typically require numerous layers, which not only adds to the expense, but block the transfer of heat from the IC dies to the exterior of the multi-chip module, thereby preventing effective cooling of the IC dies. Because these interconnectors typically require numerous layers PCB size, as well as pad and trace size become an issue.
Accordingly, there exists a need in the art to provide an economical multi-chip module that supports high speed applications
The present invention has been made in view of the above circumstances and has as an object to provide a multi-chip module having an inexpensive and reliable interconnect system.
A further object of the present invention is to provide a multi-chip module that effectively supports high speed applications.
A further object of the invention is to provide a multi-chip module capable of efficiently transfering heat from the integrated circuit dies housed within the multi-chip module to the outside of the multi-chip module.
A further object of the invention is to provide a multi-chip module in which the die interconnect component includes logic for selectively routing signals between the integrated circuit dies mounted in the multi-chip module.
A further object of the invention is to provide a multi-chip module in which the integrated circuit die interconnect component has substantially the same thermal expansion coefficient as the integrated circuit dies.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
To achieve the objects and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention comprises a multi-chip module for housing multiple integrated circuit dies that includes a housing, a plurality of electrically conductive leads held in the housing, first and second integrated circuit dies mounted within the housing, and an interconnect die mounted within the housing between the first and second integrated circuit dies. Each of the conductive leads includes an internal lead section extending within the housing and an external lead section extending outside of the housing. The interconnect die is electrically connected to the internal lead section of at least one of the electrically conductive leads. The interconnect die transmits signals between the first integrated circuit die, the second integrated circuit die, and the at least one conductive lead.
In one preferred embodiment, the interconnect die receives signals from the first integrated circuit die and outputs the received signals to the second integrated circuit die, and receives signals from the at least one conductive lead and outputs the received signals to at least one of the first and second integrated circuit dies.
The housing may include a plurality of insulative side walls that define at least a portion of the exterior surface of the housing, with the plurality of conductive leads held in the side walls, for example, in multiple, vertically-spaced tiers. The insulative side walls may receive the conductive leads in a plurality of tombstone-shaped openings.
The housing may further include an end plate joined to the insulative side walls, the end plate being formed of a heat sink material, such as copper. The first and second integrated circuit dies and the interconnect die may be mounted to the end plate.
The interconnect die may include a silicon substrate, a plurality of bonding pads, and wiring layers connecting pairs of the bonding pads. The interconnect die may include only passive components and the first and second integrated circuit dies may include active components.
The invention further comprises a multi-chip module for housing multiple integrated circuit dies that includes a housing having a plurality of insulative side walls and an end plate, where the end plate joined to the side walls to define a cavity. A plurality of electrically conductive leads are held in the side walls, each of the conductive leads includes an internal lead section extending within the cavity and an external lead section extending outside of the housing. A plurality of integrated circuit dies and a plurality of interconnect dies are mounted to the end plate within the cavity. Each interconnect die is positioned adjacent to at least two of the plurality of integrated circuit dies. Electrically conductive material electrically connects the electrically conductive leads, the integrated circuit dies, and the interconnect dies.
The electrically conductive material may couple (1) at least one of the interconnect dies to the internal lead section of at least one of the conductive leads, (2) at least one of the integrated circuit dies to the internal lead section of at least one other of the conductive leads, and (3) the integrated circuit dies to the interconnect dies. At least one of the interconnect dies may receive signals from at least one of the integrated circuit dies and output the received signals either to the electrically conductive leads or to another of the integrated circuit dies.
At least one of the interconnect dies may comprise a first bonding pad electrically coupled to a first one of the integrated circuit dies by the electrically conductive material, a second bonding pad electrically coupled to either a second one of the integrated circuit dies or one of the electrically conductive leads by the electrically conductive material, and a wiring path coupling the first bonding pad to the second bonding pad.
A first one of the interconnect dies may comprise a first bonding pad electrically coupled to a first one of the integrated circuit dies by the electrically conductive material, a second bonding pad electrically coupled to a third bonding pad of a second one of the interconnect dies by the electrically conductive material, and a wiring path coupling the first bonding pad to the second bonding pad. The second one of the interconnect dies may comprise the third bonding pad, a fourth bonding pad electrically coupled to either a second one of the integrated circuit dies or one of the conductive leads by the electrically conductive material, and a wiring path coupling the third bonding pad to the fourth bonding pad.
The invention further comprises a multi-chip module for housing multiple integrated circuit dies including a housing having a plurality of insulative side walls and an end plate joining the side walls to define a cavity, a plurality of electrically conductive leads held in the side walls, first, second, third, and fourth integrated circuit dies mounted to the end plate within the cavity, first, second, third, and fourth interconnect dies mounted to the end plate within the cavity, and electrically conductive material coupling the conductive leads and the interconnect dies, the conductive leads and the integrated circuit dies, and the integrated circuit dies and the interconnect dies. Each of the conductive leads include an internal lead section extending within the cavity and an external lead section extending outside of the housing. In addition, the first interconnect die is mounted between the first and second integrated circuit dies, the second interconnect die mounted between the second and third integrated circuit dies, the third interconnect die mounted between the third and fourth integrated circuit dies, and the fourth interconnect die mounted between the first and fourth integrated circuit dies.
Each of the interconnect dies may comprise a silicon substrate. The housing may include four side walls joined together in a rectangular shape and the first, second, third, and fourth integrated circuit dies may be mounted to the end plate adjacent the corners of the side walls, respectively. The interconnect dies may be rectangular-shaped, with the first and third interconnect dies positioned end-to-end with respect to each other and the second and fourth interconnect dies positioned end-to-end with respect to each other and separating the first and third interconnect dies.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.